Electronic design automation (EDA) tools are used to design electronic circuits used in a variety of electronic systems, such as, for example, printed circuit boards (PCBs) and integrated circuits (ICs). When using an EDA tool to design electronic circuits, the electronic circuit designs are simulated and the results of the simulations are analyzed to check the integrity of the designs and predict their behavior. For example, Simulation Program with Integrated Circuit Emphasis (SPICE) is a software program often used with EDA tools to simulate IC and PCB-level circuit designs to check their integrity and predict their behavior.
Depending on the complexity of the circuit design and the type of simulation being performed, the simulations can take a long period of time to perform. Parallel circuit simulation techniques are currently used by EDA tools to reduce the time period required to perform circuit simulations. For example, it is known to decompose a circuit simulation task into sub-tasks, assign each sub-task to one of a plurality of central processing unit (CPU) cores and to perform the sub-tasks in parallel on the CPU cores. Such techniques are very effective at reducing simulation times for very large circuit designs, but are not as beneficial for smaller circuit designs.
One known parallelization technique seeks to reduce simulation times for transient circuits having short memories. The technique, disclosed in an article entitled “Time-Domain Segmentation based Massively Parallel Simulation for ADCs”, by Wu, et al, published in Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, May 29, 2013-Jun. 7, 2013, comprises partitioning a transient simulation task into n segments of equal lengths of time, overlapping adjacent segments by an overlap time, Tov, performing transient simulations for all of the segments concurrently in respective CPU cores, and then conjoining the resulting waveforms while discarding the Tov beginning portion of each waveform except for the first waveform. Because transient circuits have memory, it necessary to overlap adjacent segments to account for memory effects. The overlap time Tov is determined algorithmically by performing an iterative algorithm comprising: (1) initially setting Tov to zero or some other value; (2) performing the above-described simulation and determining whether adjacent resulting waveforms have converged; (3) if they have not converged, incrementing the value of Tov and performing steps (2) and (3) until convergence of adjacent waveforms has been verified. The value of Tov at which convergence was verified is then used as Tov during actual simulation.
One of the disadvantages of the technique disclosed in Wu, et al. is that the process of determining the appropriate overlap time Tov is time consuming. It would be advantageous to provide an EDA system and method that allow the overlap time Tov to be quickly and accurately determined without having to perform the above-described iterative process.